1. Field the Invention
The invention relates generally to microcomputer systems and more particularly to instruments that enable the development and debugging of the hardware and software in target machines by the emulation and control of the target CPU within the target environment.
2. Description the Prior Art
In circuit emulation (ICE) of microcomputers for target system development is popular and well known in the microcomputer system industry. ICE development tools have been available for several years from Step Engineering (Sunnyvale, Calif.), Intel Corporation (Santa Clara, Calif.), Motorola Microsystems (Tempe, Ariz.), and others.
Microprocessor chips are complex devices requiring that both their hardware and software environments to be near perfect for proper operation. When a new microcomputer chip is first introduced, for example the i960 RISC processor by Intel or the 68040 CISC processor by Motorola, compatible hardware and software target environments do not exist and must be developed rapidly. This poses some difficulty because the timing is such that this coincides with a time when expertise in those particular environments is low. Since the chip is new, a very limited number of engineers have any direct experience with it. The job of designing a new system that uses the latest microprocessor is extremely difficult and often paces the ability of a manufacturer to compete effectively in its respective market. ICE system tools help get new designs off the ground by allowing incremental hardware and software development and a convenient cross-assembler and downloading mechanism for target object modules.
As the microprocessor art has advanced, clock speeds have become relatively faster and word widths wider. An early ICE from Intel, sold as the MDS ICE-85 in the late 1970s, had an eight-bit data width and a five-megahertz clock. In the 1990s, data widths of 32 bits are routine, and clock speeds around 50 MHz. Initially, target processors could be relocated in the ICE and attached to the target system via an umbilical of woven or twisted wires. When clock speeds got too high for this, the target processors were left in the target systems, and had adaptors that plugged between the target processor and the target system to intercept and/or sense key signals. These signals were then buffered by a buffer box located at the target end of a cable extending back to the main unit of the ICE. Most flat cables do not work well at high speeds and some attempts were made to use coaxial cables. But with over 100 signals to communicate, use of coax cables is not practical. A few systems use flexible printed circuits with buried ground planes to interconnect the main chassis of an ICE system umbilically to its target processor buffer box. These prior art systems suffer from poor mechanical and electrical transitions between the processor and the flex, the flex and the buffer box, and the flex between the main chassis and the buffer box.
Wider data and address widths have also caused a competition between data, address, and control signals and processor status for pinouts in the device package. System designers decoded these pins to track program execution in real-time. Internal cache memories have fundamentally obfuscated the visibility system designers once had into the internal operations of a microprocessor. For those reasons, microprocessor manufacturers have produced special "bond-out" chips that resemble the standard versions of their respective parts, but the bond-outs have special pins, and sometimes whole buses, that give a system developer some visibility into the internal workings of the processor (and inside the cache). The view, however, is not as clear as one would hope for, and special devices and programs are needed to decode and give meaning to the hints provided at the special bond-out interfaces.